The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. Avalon® Memory-Mapped Interface Signals 6. we should see DLLP packets on the interface. 1G/2. Figure 1. The present clauses in 802. 14. 2019年2月12日 閲覧。 ^ “Serial-GMII Specification” (2005年4月27日). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. While the XGMII is an optional interface, it is used extensively in this standard as a basis for functional specification and provides a common service interface for Clauses 47, 48, and 49. Return to the SSTL specifications of Draft 1. to the PCS synchronization specification. 1 of the IEEE P802. 2. Serial Interface Signals 6. Device Family Support 2. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. 8. In each table, each row describes a test case. standard FR-4 material. 17. This table shows the mapping of this non-standard format to the standard SDR XGMII interface. normal signal, the XGMII input is ignored until PCS_Test. Introduction. TXC<3:0> and RXC<3:0> are the data delimiters for these four byte lanes and separate frame data bytes from controlThe limitation on the clock speed was due to the capacitive load associated with having 32 bi-directional pins on an MDIO bus. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 3-2008 specification. 5GPII Word For off chip stuff, these days nobody uses XGMII, it's either XAUI (4x3. . All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at Data Input/Output (MDIO) interface Clause 46. 3 standard. 3. Router with two dozen 10 Gigabit Ethernet ports and three types of physical-layer module. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 802. This specification is targeted towards the requirements of embedded systems. The RGMII interface can be either a MAC interface or a media interface. MAC – PHY XLGMII or CGMII Interface. There is actual code in here. XGMII Signals The XGMII supports 10GbE at 156. For Ethernet backplane applications, XGMII compliant 10GBASEKR_PHY soft IP is developed. About LL Ethernet 10G MAC x 1. Each lane contains 8 data plus 1 control bits. Previous definition/implementations cover single (SGMII) and quad (QSGMII) options. 5 Gb/s and 5 Gb/s as well as 10 Gb/s. The modules are capable of operating with XGMII interface widths of 32 or 64 bits. The data is separated into a table per device family. PHY /Link interface specification , . We kept the speed low to make sure that this would be a non-challenging interface. Application. XAUI and XGMII Layers Section Content Transceiver Datapath in a XAUI Configuration XAUI Supported Features Transceiver Clocking and Channel Placement. By grouping them in a QSGMII, only one SERDES interface is needed to be used, so only 1 Tx and 1 Rx (2 in total) differential lines are routed. 1. - Deficit Idle Count per Clause 46. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 49. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. 3-2008, defines the 32-bit data and 4-bit wide control character. 1. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. Labels: Labels: Network Management; usxgmii. September 23, 2021 Product Specification Rev1. 1. For more information on XAUI, please refer. XGMII/GMII/RGMII: Source And Data Centered I/O Timing Modes; Supports Jumbo Packet (9600 byte maximum) Operation. 1G/10GbE GMII PCS Registers 5. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. When TCP/IP network is applied in. 3 Clause 49 BASE-R physical coding sublayer/physical The 10GBASE-R PHY uses the XGMII interface to connect to the IEEE802. The Serial Gigabit Media Independent Interface ( SGMII) is a sequel of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. Well I disagree with the technical information on a functional specification. 14. Getting Started x 3. The host layer access to the Controller IP for Automotive is through industry-standard AXI or AHB interfaces when the DMA is being used or through an external FIFO interface. 3ab standard. In this demo, the FiFo_wrapper_top module provides this interface. 10 Gigabit Attachment Unit Interface (XAUI / ˈ z aʊ i / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802. O-RAN can. specification for internal use only. relevant amba specification accompanying this licence. We are using the Yocto Linux SDK. 5. 1G/10GbE PHY Register Definitions 5. 49. 1G/10GbE Control and Status Interfaces 5. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE Electrical Spec (no PMA) IEEE Specifications • 3. 8. XGMII Signals 6. 1. Figure 3: 10GBASE-X PHY Structure. The 5GBASE-R PCS provides all services required by the XGMII including Encoding (decoding) of XGMII data octets to (from) 64B/66B blocks for communication with the underlying PMA. The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge LogiCORE™ which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. Small Form-factor Pluggable connected to a pair of fiber-optic cables. 5. 5Gb/s 8B/10B encoded - 3. IEEE 802. 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. 2 PCIE Interface PCI Express Gen3: Single port X4 lanes Compliant with PCI Express Base Specification Rev. This is the ACPI _DSD Implementation Guide. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. The XGMII Controller interface block interfaces with the Data rate adaptation block. 3-2008 and the IEEE802. Resource Utilization 3. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which. 5. At the transmit side of the XAUI interface, the data and control characters are converted within the XGXS into an 8B/10B encoded data stream. mode, all the interface pins of 4 CPs in a cluster can be combined and used together to implement an 8-bit interface required by GMII. XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between. reference design for SGMII at 2. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. 201. 3) 10 Gb/s Serial Electrical Interface Bit serial @ 10Gb/s 64B/66B encoded - 10. Media Independent Interface ( MII )，介质独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. 5. XGMII interface in my view will be short lived. AMD provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. XGMII stands for X(roman 10)-G-Media-Independant-Interface which is IEEE 802. It can also be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The NVMe ® Management Interface (NVMe-MI™) specification was created to define a command set and architecture for managing NVMe storage, making it possible to discover, monitor, configure, and update NVMe devices in multiple operating environments. 1G/2. 4. (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. SD 4. However, if the XGMII is not implemented, a conforming implementation must behave functionally as though the RS and XGMII were present. The XCM . 0 that is designed to support both the device family using the IOD blocks used with GPIO or HSIO buffers. Configuration Registers Description x. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device. 5M transfers/s) • PHY line rate is preserved (10. 3 Clause 46, is the main access to the 10G Ethernet physical layer. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. 3-2008, defines the 32-bit data and 4-bit wide control character. PHY x. 1. Table 20. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. 25 Gbps). 5G/1G Multi-Speed. The XgmiiSource drives XGMII traffic into a design. (See IEEE Std 802. The IP supports 64-bit wide data path interface only. AVST-XGMII – monitor the packet condition at client Avalon-ST and XGMII interface a. It is a straightforward implementation detail to select either AC or DC. Table 1. 4. The data are multiplexing to 4 lanes in the physical layer. CPRI Intel® FPGA IP core contains the logic for Ethernet PCS. Check Link Fault status signal, value 01 (Local Fault). 3125 Gbps/32-bit = 322. // Documentation Portal . Interface XGMII/ GMII/MII External PHY Serial Interface. 5 volts per EIA/JESD8-6 and select from the options > within that specification. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. XGMII Interface 10G 32-bit MODE(MAC+ $;, /LWH :UDSSHU SERDES DATA MUX. This PHY IP core is made available as part of the transceiver functionality of the Intel® FPGAs. Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following requirements: • Convey network data and port speed between a 10/100/1000 PHY and a MAC with significantly less signal pins than required for GMII. 3125 Gb/s link. // Documentation Portal . The TLK3134 provides high-speed bidirectional point-to-point data transmissions with up to 30 Gbps of raw data transmission capacity. 5 V MDIO I/O) RGMII. XGMII Signals 6. Please refer to PG210. This module converts XGMII interface of XGMAC core to high speed serial interface needed by physical interface. PCS Registers 5. VIP Options. These published antenna patterns and associated Institute of. 3. I would not want to retain the current electrical specification. Additionally, for applications requiring 20 Gbps throughput, Intel FPGA's XAUI PHY solution can support DXAUI (4 x 6. ÐÏ à¡± á> þÿ. We would like to show you a description here but the site won’t allow us. Features 2. 1. "JUST" <smile>. the official core works at 1Gbps, and the MGT can be configured tow work at 2. The interface in Java is a mechanism to achieve abstraction. 0 Cards use the UHS-II bus interface, which features two rows of pins rather than the single row found in UHS-I. Connection to the SerDes is through a configu-rable 16-, 20-, 32-, 40-, or 64-bit interface. 1. 125Gbps SERDES available at Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. 4. 4. Device Family Support 2. The 10G Ethernet Verification IP is compliant with IEEE 802. , the received data. e. 3bz-2016 amending the XGMII specification to support operation at 2. PHY Registers. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. > 3. 3 are described in terms of two primary interfaces Medium dependent interface (MDI) Media independent interface (MII) While the MDI is visible to the user, and usually tightly specified, the MII is often used simply as a convenient way to partition the physical layer specifications from thedocument, we will use the term “GMII” to cover all of the specification regarding the MII interface. Reconfiguration Signals 6. 125 Gbps) or XFI (1x10. 3, Clause 47. Unidirectional. 11. interface is the XGMII that is defined in Clause 46. 2023年11月1日 閲覧。 ^ “QSGMII Specification” (2009年7月20日). MAU. The Universal Serial Gigabit Media Independent Interface (USGMII) is an extension of the current SGMII and QSGMII. 本文非原创，摘自：Media Independent Interface Media Independent Interface ( MII)，媒体独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. The waveform below shows a DLLP packet. The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2. > > 1. Host Interface Speed Data width # Pins Clock Frequency Transmission Specification QSGMII 4x ≤1. 5Gbps but can't find any reference design for it. Signal. 1. PHY. Is there a reference design for for SGMII to GMII core at 2. 5 volts per EIA/JESD8-6 and select from the options > within that specification. There are a total of 28 pins within a cluster, so each cluster has enough signals to implement one GMII interface. XGMII Encapsulation 4. 3 CSMA/CD LAN Model As noted earlier, the XGMII interface consists of 4 lanes of 8 bits. 3z specification. 6. 5G, 5G, or 10GE data rates over a 10. Uses device-specific transceivers for the RXAUI interface. 16. The subsidized sponsorship of standards via the IEEE GET Program helps expand the global reach of technical knowledge developed by industry, accelerates adoption of IEEE standards, contributes to an open knowledge community, promulgates open information exchange to foster innovation, and connects the IEEE brand with the development of. However, Intel FPGAs do not comply with or support these interface specifications to directly interface with the required twisted-pair copper cables such as CAT-5/6/7. Designed to meet the USXGMII specification EDCS-1467841 revision 1. standard FR-4 material. Release Information 2. L- and H-Tile Transceiver PHY User Guide. The IP core is compatible with the RGMII specification v2. - Wishbone Interface for control. . 5 volts per EIA/JESD8-6 and select from the options > within that specification. 7. 3 media access control (MAC) and reconciliation sublayer (RS). Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802. 0 > 2. . The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. 25 MHz interface clock. (See IEEE Std 802. 3. All forum topics; Previous Topic; Next Topic; 4 Replies 4. Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications. 25MHz PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156. 25MHz, DDR) XGTMII[35:0] Output XGMII Transmit Data and Control Signals. This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. 3-2008 specification. GMII- Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000. 802. For D1. PLS. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination. Release Information 2. Figure 2-3: Ethernet 1/10G Dynamically Switching 32-bit PCS/PMA IP Block Diagram. interface ERC721TokenReceiver {/// @notice Handle the receipt of an NFT /// @dev The ERC721 smart contract calls this function on the recipient /// after a `transfer`. Reconfiguration Signals 6. Simulation and signal. Physical. 3 is silent in this respect for 2. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. Configuration of the core is done through a configuration vector. 3125 Gbps serial line rate with 64B/66B encoding. This revision offers architecture diagram of Non-RT RIC, collects requirements on the Non-RT RIC framework, Non-RT RIC logical functions and services of the R1 interface. An SFP interface on networking hardware is a modular slot for a media-specific transceiver, such as for a fiber-optic cable. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device. 3ba specifications and verifies MAC-to-PHY layer interfaces of designs with a 100G Ethernet interface CGMII. 5. > 3. Reference HSTL at 1. Table of Contents IPUG115_1. RGMII, XGMII, SGMII, or USXGMII. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. 32 Gbps over a copper or optical media interface. They call this feature AQRate. Performance and Resource. ファイバーチャネル・オーバー・イーサネット. – Make MDIO/MDC part of each optional interface (XGMII, XAUI, XSBI, SUPI) • Any device with one of these interfaces would have to also implement MDIO/MDCIEEE 1588v2 Timestamp Interface Signals 7. by clicking “i agree” or otherwise using or copying the relevant amba specification you indicate that you agree to be bound by all the terms of this licence. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. Hardware and Software Requirements. According to IEEE802. Configuration Registers A. The PHY side of the MAC implements the XLGMII or CGMII protocol as defined by the IEEE 802. Application. Serial Data Interface 5. 8. According to the GigE vision specification, the device registers are described in the xml file. RXAUI. 5G、5G、または 10GE のシングル ポートを使用するメカニズムを持つ Ethernet Media Access Controller (MAC) を実装します。(1) The reconciliation sublayer (RS) interfaces the serial MAC data stream and the parallel data of XGMII. LL Ethernet 10G MAC Operating Modes 1. PCS) IP GT IP Serial. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. PMA. Received Ethernet bytes are available on the 64-bit XGMII interface (RX_MII_D/C). 3-2008 specification. 10 Gigabit Ethernet MAC The 10 Gigabit Ethernet MAC core connects to the PHY layer through an external XGMII. More specifically, physical (PHY) layer 227 provides electrical and physical specifications, including details like pin layouts and signal voltages, for interactions between network device 110 and physical channel 120. The TLK2206 supports both 4/5-bit RTBI as well as 8/10-bit parallel interface using DDR clocking. Fair and Open Competition. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. 3 の第 49 項で定義されている BASE-R PCS/PHY (Physical Coding Sublayer/Physical Layer) を採用し、10M、100M、1G、2. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. 4 PHYs defined in IEEE Std 802. 15. In this demo, the FiFo_wrapper_top module provides this interface. 5x faster (modified) 2. 3 Clause 46 ratified specification enabling a variety of PHY and MAC chips. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. XGMII Data Interface Signals XGTMIICLK Output XGMII Transmit Clock (156. Designed to Dune Networks RXAUI specification. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. Headlight. •400 Gb/s Ethernet • Support a MAC data rate of 400 Gb/s • Support a BER of better than or equal to 10^-13 at the MAC/PLS service interface (or the frame loss ratio equivalent) for 400 Gb/sBeginner. Register Map 7. 2. The Barrel Shifter looks for the start of frame delimiters on 32-bit boundary and re-aligns the data on 64-bit boundary. Front-Light Manager. According to IEEE802. 3. TOD Interface Signals. 1 Capacity and LBA count 10 2. 0 - January 2010) Agenda IEEE 802. 4 Benefits of XAUI to 10GbE • Provided the industry with a starting point – low cost, common interface for discrete / pluggable components commonly used in 10G Ethernet Systems – Prevented significant segmentation which would have delayed deployment & resulted in higher cost – Provided a standard based mechanism to communicate 10Gb/s over. 25GMII is similiar to XGMII. USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. Core data width is the width of the data path connected to the USXGMII IP. • Once in PCS_Test, there is a problem if the MAC signals LPI over the XGMII interface since this can initiate a transition to QUIET before the Link Partner PHY is ready. There are five workstreams that comprise DC-MHS. XAUI addresses several physical limitations of the XGMII. Reference HSTL at 1. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. Use Case ‘Front Light Management’: Exchange Type of Front Light. 5 volts per EIA/JESD8-6 and select from the options > within that specification. This block contains the signals TXD (64. Key Specifications Function Data Rate Serial I/F Parallel I/F Power Special FeaturesSGMII supports a single 10M/100M/1G network port over 1,25Gbps SERDES between MAC and PHY, while QSGMII supports four 10M/100M/1G network ports over 5Gbps SERDES between MAC and PHY. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including: xgmii_tx[] Use legacy Ethernet 10G MAC XGMII interface enabled. 3-2008 specification. Reconfiguration Signals 6. The test parameters include the part information and the core-specific configuration parameters. XGMII Signals 6. Local fault happens, all data sent by client user logic are dropped. Table 13. Notably, MII 370 is an interface capable of providing two-way communication between MAC device 350 and PHY device 360. The 10 Gigabit Ethernet IP core is designed for applications such as integrated networking devices. 125Gbps for the XAUI interface. The Gigabit-Ethernet media independent interface (GMII) specified by IEEE802. However, the Altera implementation uses a wider bus interface in connecting a. Interface (XGMII) 46. 3125 Gbps serial line rate with 64B/66B encoding. Getting Started x 3. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. Code replication/removal of lower rates onto the 10GE link. You are required to use an external PHY device to. © 2012 Lattice Semiconductor Corp. 25G-AUI is a single lane version of the C2C and C2M electrical interfaces defined in 802. 3 is used as the interface between an Ethernet physical layer device and a media access controller. Figure 46–1 shows the relationship of the RS and XGMII to the ISO/IEC (IEEE) OSI reference model. Release Information 1. XGMII & XAUI Relationship to ISO/IEC Open Systems Interconnection (OSI) Reference Model & IEEE 802. Designed to Dune Networks RXAUI specification. The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge AMD LogiCORE which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. 7. 0. Each (MAC) with a XGMII (10 Gigabit Media Independent Interface) for incorporation in a customer’s ASIC design. 3) enabled Pattern Gen code for continues sending of packet . 4. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. The Universal Serial Gigabit Media Independent Interface (USGMII) is an extension of the current SGMII and QSGMII. 3. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 4. Uses two transceivers at 6. 19. 8. The BCM84885 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, crosstalk cancelers, and all required support circuitry. The original single row of pins is compatible. The MII interface is always a MAC interface which is typically connected to an Ethernet MAC device. 5V LVDS signal pair to support high-speed mode and one 1. 3 10 Gbps Ethernet standard. Small Form-factor Pluggable connected to a pair of fiber-optic cables. . 5. MDI. This block. 3ae 10 Gigabit Ethernet Summary n The XGMII coding proposal is stable n The EIA/JEDEC SSTL_2 standard can be referenced for the XGMII electrical specification n The timing proposal presented herein is a starting point for further discussion 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. 4. PMA – Physical medium attachment. GMII- Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. Hot Swap Schroff cPCI backplanes fulfill the requirements for Basic Hot Swap of the Hot Swap Specification PICMG 2. Avalon® Memory-Mapped Interface Signals 6. Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist. Supports 10-Gigabit Fibre Channel (10. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP\+ optical module using SFI electrical specification. 3125 Gbps). Want to thank TFD for its existence? Tell a friend about us, add a link to this page, or visit the webmaster's page for free fun content. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including:Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. . XAUI Align Character Skew Support of 30 Bit Times at Chip Pins; MDIO: IEEE 802. MDI – Media dependant interface.